module UART_RXer (
    clk,
    res,
    RX,
    data_out,
    en_data_out
);

input       clk;
input       res;
input       RX;
output[7:0] data_out;//接收数据输出
output      en_data_out;//输出使能 

reg[7:0] state;//状态机
reg[12:0] cont;//计数一位宽度
reg[3:0]  contbit;//计数位数 
reg       RX_delay;//

reg en_data_out;
reg[7:0] data_out;

always @(posedge clk or negedge res) begin
    if (res==0) begin
        state<=0;
        cont<=0;   
        RX_delay<=0;
        data_out<=0; 
        en_data_out<=0;   
    end else begin
        RX_delay<=RX;
        case (state)
            0://等空闲
                begin
                    if (cont==49) begin
                        cont<=0;
                    end else begin
                        cont<=cont+1;
                    end

                    if (cont==0) begin
                        if (RX==1) begin
                            contbit<=contbit+1;
                        end else begin
                            contbit<=0;
                        end   
                    end

                    if (contbit==10) begin
                        state<=1;
                    end
                end
            1://等起始位
                begin
                    en_data_out<=0;
                    if (~RX&RX_delay) begin
                        state<=2;
                    end
                end
            2://接收D0
                begin
                    if (cont==75-1) begin
                        cont<=0;
                        data_out[0]<=RX;
                        state<=3;
                    end else begin
                        cont<=cont+1;
                    end
                end
            3: //接受D1
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[1]<=RX;
                        state<=4;
                    end else begin
                        cont<=cont+1;
                    end                    
                end
            4: //接受D2
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[2]<=RX;
                        state<=5;
                    end else begin
                        cont<=cont+1;
                    end                    
                end
            5: //接受D3
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[3]<=RX;
                        state<=6;
                    end else begin
                        cont<=cont+1;
                    end                    
                end
            6: //接受D4
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[4]<=RX;
                        state<=7;
                    end else begin
                        cont<=cont+1;
                    end                    
                end
            7: //接受D5
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[5]<=RX;
                        state<=8;
                    end else begin
                        cont<=cont+1;
                    end                    
                end  
            8: //接受D6
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[6]<=RX;
                        state<=9;
                    end else begin
                        cont<=cont+1;
                    end                    
                end
            9: //接受D7
                begin
                    if (cont==50-1) begin
                        cont<=0;
                        data_out[7]<=RX;
                        state<=10;
                    end else begin
                        cont<=cont+1;
                    end                    
                end 
            10://产生使能信号
                begin
                    en_data_out<=1;
                    state<=1;
                end     
            default:
                begin
                    state<=0;
                    cont<=0;
                    contbit<=0;
                    en_data_out<=0;
                end                                                                                                 
        endcase
    end
end

endmodule


module UART_RXer_tb ();
reg clk;
reg res;
wire RX;
wire[7:0] data_out;
wire en_data_out;
reg[25:0] RX_send;//串口发送数据 
UART_RXer UART_RXer (
    clk,
    res,
    RX,
    data_out,
    en_data_out
);//同名例化
reg [12:0] cont;
assign RX=RX_send[0];
initial begin
            clk<=0;res<=0;RX_send<={1'b1,8'b10011011,1'b0,16'hffff};
            cont<=0;
    #17     res<=1;
    #900000000  $stop;
end

always #5 clk<=~clk;


always @(posedge clk) begin
    if (cont==50-1) begin
        cont<=0;
        RX_send<={RX_send[0],RX_send[25:1]};
    end else begin
        cont<=cont+1;
    end
    
end



endmodule
